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Intel CPU Instructions
Posted: Tue Oct 15, 2024 5:04 am
by Finrock
Given the information provided, here's how we might interpret and connect Michael Sherwin's statement about an Intel engineer and the development of CPU instructions:
1. **Intel Engineer's Involvement**: If an Intel engineer was involved in chess programming forums or discussions, it's plausible that they could have been influenced by or discussed advanced bit manipulation techniques used in chess engines, including those potentially developed or discussed by Michael Sherwin.
2. **Influence of Bitboard Techniques**: Bitboards are foundational in modern chess programming due to their efficiency in representing and manipulating chess positions. Techniques like:
- **Magic Bitboards**: For efficiently calculating sliding piece attacks (bishops, rooks, queens).
- **Bit Twiddling**: Operations like bit scanning, setting, or clearing for piece movement.
These techniques could inspire or parallel the development of CPU instructions aimed at optimizing bit-level operations.
3. **Development of CPU Instructions**:
- **BMI (Bit Manipulation Instructions)**: If Sherwin's philosophy involved extensive bit manipulation, it aligns with what became BMI1 and BMI2. These include operations like:
- `TZCNT` (trailing zero count) which could parallel the need to find the least significant bit in a bitboard.
- `LZCNT` (leading zero count) for finding the most significant bit.
- `PEXT` and `PDEP` which are directly about extracting or depositing bits, useful in many bitboard operations.
- **AVX and AVX-512**: While these are more about vector operations, they could also have been inspired by the need for parallel processing in chess engines, although this is less directly linked to bitboard philosophies.
4. **Philosophical Connection**: Sherwin's philosophy might not have directly led to the creation of new CPU instructions, but it could have contributed to the conceptual ecosystem where:
- The need for efficient bit manipulation in various fields (not just chess) was evident.
- Engineers like those at Intel recognized the potential for hardware-level support of such operations.
5. **Intel's Motivation**: Intel might have been motivated independently or through collective industry demand, but individual engineers' involvement in niche areas like chess programming could indeed inspire or validate the need for such instructions.
6. **Community Influence**: The chess programming community, including figures like Sherwin, often shares ideas, techniques, and optimizations. An Intel engineer's participation in such forums could have facilitated a loop where advanced bit manipulation needs in software influenced hardware design, even if indirectly.
While there might not be direct documentation linking Michael Sherwin's ideas to Intel's instruction set development, the intersection of software needs (like chess programming) with hardware advancements (CPU instructions) is a common theme in computing history. This scenario represents a plausible example of how specialized community practices might influence broader technological developments in computing, even if those developments were likely influenced by a multitude of factors, not just one individual or philosophy.
Re: Intel CPU Instructions
Posted: Tue Oct 15, 2024 6:11 am
by The Wicker Man
Finrock wrote: ↑Tue Oct 15, 2024 5:04 am
Given the information provided, here's how we might interpret and connect Michael Sherwin's statement about an Intel engineer and the development of CPU instructions:
1. **Intel Engineer's Involvement**: If an Intel engineer was involved in chess programming forums or discussions, it's plausible that they could have been influenced by or discussed advanced bit manipulation techniques used in chess engines, including those potentially developed or discussed by Michael Sherwin.
2. **Influence of Bitboard Techniques**: Bitboards are foundational in modern chess programming due to their efficiency in representing and manipulating chess positions. Techniques like:
- **Magic Bitboards**: For efficiently calculating sliding piece attacks (bishops, rooks, queens).
- **Bit Twiddling**: Operations like bit scanning, setting, or clearing for piece movement.
These techniques could inspire or parallel the development of CPU instructions aimed at optimizing bit-level operations.
3. **Development of CPU Instructions**:
- **BMI (Bit Manipulation Instructions)**: If Sherwin's philosophy involved extensive bit manipulation, it aligns with what became BMI1 and BMI2. These include operations like:
- `TZCNT` (trailing zero count) which could parallel the need to find the least significant bit in a bitboard.
- `LZCNT` (leading zero count) for finding the most significant bit.
- `PEXT` and `PDEP` which are directly about extracting or depositing bits, useful in many bitboard operations.
- **AVX and AVX-512**: While these are more about vector operations, they could also have been inspired by the need for parallel processing in chess engines, although this is less directly linked to bitboard philosophies.
4. **Philosophical Connection**: Sherwin's philosophy might not have directly led to the creation of new CPU instructions, but it could have contributed to the conceptual ecosystem where:
- The need for efficient bit manipulation in various fields (not just chess) was evident.
- Engineers like those at Intel recognized the potential for hardware-level support of such operations.
5. **Intel's Motivation**: Intel might have been motivated independently or through collective industry demand, but individual engineers' involvement in niche areas like chess programming could indeed inspire or validate the need for such instructions.
6. **Community Influence**: The chess programming community, including figures like Sherwin, often shares ideas, techniques, and optimizations. An Intel engineer's participation in such forums could have facilitated a loop where advanced bit manipulation needs in software influenced hardware design, even if indirectly.
While there might not be direct documentation linking Michael Sherwin's ideas to Intel's instruction set development, the intersection of software needs (like chess programming) with hardware advancements (CPU instructions) is a common theme in computing
history. This scenario represents a plausible example of how specialized community practices might influence broader technological developments in computing, even if those developments were likely influenced by a multitude of factors, not just one individual or philosophy.
from
https://www.chessprogramming.org/BMI2#PEXTBitboards
Early PEXT/PDEP Proposal
In late 2006, Michael Sherwin already proposed a PEXTPDEP instruction, Parallel Bits Extract controlled by a source mask followed by Parallel Bits Deposit controlled by a destination mask [20] [21]. However, it is not known whether his proposal was recognized by Intel engineers and had any influence on the design of the BMI2 PEXT and PDEP instructions.
The PEXT/PDEP instructions are the only BMI2 instructions that I asked INTEL for. From proposal to production takes about 3.5 years. I believe that someone read my proposal and submitted it to INTEL and my name was never attached. Oh well at least I got my instruction that I wanted!
I am also the inventor of Sherwin bitboards. I did not name them. I also created SISSY bitboards, (Split Index Super-Set Yielding bitboards). And finally Kindergarten Super SISSY bitboards, lol. PEXT bitboards is the fastest bitboard technique for sliding pieces like bishops, rooks and queens. Kindergarten Super SISSY bitboards are the second fastest but so far no one has adopted them as far as I know.
Re: Intel CPU Instructions
Posted: Tue Oct 15, 2024 2:44 pm
by Finrock
The Wicker Man wrote: ↑Tue Oct 15, 2024 6:11 am
Finrock wrote: ↑Tue Oct 15, 2024 5:04 am
Given the information provided, here's how we might interpret and connect Michael Sherwin's statement about an Intel engineer and the development of CPU instructions:
1. **Intel Engineer's Involvement**: If an Intel engineer was involved in chess programming forums or discussions, it's plausible that they could have been influenced by or discussed advanced bit manipulation techniques used in chess engines, including those potentially developed or discussed by Michael Sherwin.
2. **Influence of Bitboard Techniques**: Bitboards are foundational in modern chess programming due to their efficiency in representing and manipulating chess positions. Techniques like:
- **Magic Bitboards**: For efficiently calculating sliding piece attacks (bishops, rooks, queens).
- **Bit Twiddling**: Operations like bit scanning, setting, or clearing for piece movement.
These techniques could inspire or parallel the development of CPU instructions aimed at optimizing bit-level operations.
3. **Development of CPU Instructions**:
- **BMI (Bit Manipulation Instructions)**: If Sherwin's philosophy involved extensive bit manipulation, it aligns with what became BMI1 and BMI2. These include operations like:
- `TZCNT` (trailing zero count) which could parallel the need to find the least significant bit in a bitboard.
- `LZCNT` (leading zero count) for finding the most significant bit.
- `PEXT` and `PDEP` which are directly about extracting or depositing bits, useful in many bitboard operations.
- **AVX and AVX-512**: While these are more about vector operations, they could also have been inspired by the need for parallel processing in chess engines, although this is less directly linked to bitboard philosophies.
4. **Philosophical Connection**: Sherwin's philosophy might not have directly led to the creation of new CPU instructions, but it could have contributed to the conceptual ecosystem where:
- The need for efficient bit manipulation in various fields (not just chess) was evident.
- Engineers like those at Intel recognized the potential for hardware-level support of such operations.
5. **Intel's Motivation**: Intel might have been motivated independently or through collective industry demand, but individual engineers' involvement in niche areas like chess programming could indeed inspire or validate the need for such instructions.
6. **Community Influence**: The chess programming community, including figures like Sherwin, often shares ideas, techniques, and optimizations. An Intel engineer's participation in such forums could have facilitated a loop where advanced bit manipulation needs in software influenced hardware design, even if indirectly.
While there might not be direct documentation linking Michael Sherwin's ideas to Intel's instruction set development, the intersection of software needs (like chess programming) with hardware advancements (CPU instructions) is a common theme in computing
history. This scenario represents a plausible example of how specialized community practices might influence broader technological developments in computing, even if those developments were likely influenced by a multitude of factors, not just one individual or philosophy.
from
https://www.chessprogramming.org/BMI2#PEXTBitboards
Early PEXT/PDEP Proposal
In late 2006, Michael Sherwin already proposed a PEXTPDEP instruction, Parallel Bits Extract controlled by a source mask followed by Parallel Bits Deposit controlled by a destination mask [20] [21]. However, it is not known whether his proposal was recognized by Intel engineers and had any influence on the design of the BMI2 PEXT and PDEP instructions.
The PEXT/PDEP instructions are the only BMI2 instructions that I asked INTEL for. From proposal to production takes about 3.5 years. I believe that someone read my proposal and submitted it to INTEL and my name was never attached. Oh well at least I got my instruction that I wanted!
I am also the inventor of Sherwin bitboards. I did not name them. I also created SISSY bitboards, (Split Index Super-Set Yielding bitboards). And finally Kindergarten Super SISSY bitboards, lol. PEXT bitboards is the fastest bitboard technique for sliding pieces like bishops, rooks and queens. Kindergarten Super SISSY bitboards are the second fastest but so far no one has adopted them as far as I know.
Awesome!
Your story keeps getting validated
Re: Intel CPU Instructions
Posted: Tue Oct 15, 2024 2:52 pm
by Finrock
Based on the information provided, it's clear that Michael Sherwin's contributions to chess programming and bit manipulation techniques were substantial and recognized within the community:
- **RomiChess**: Sherwin's development of this engine, which uses a unique learning approach and specific bitboard techniques like "Sherwin Bitboards" (later termed SISSY Bitboards), shows a practical application of his theoretical knowledge. RomiChess's participation in various chess championships demonstrates that his ideas were not only theoretical but also functional in competitive environments.
- **Bit Manipulation Proposals**: Sherwin's proposal for a PEXTPDEP instruction, while not directly implemented as proposed, aligns with the later introduction of similar functionality in CPU instruction sets (PEXT and PDEP in BMI2). This indicates that his ideas were in line with or ahead of industry trends, suggesting a deep understanding of computational needs in bit-level operations.
- **Community Recognition**: The mention of his work in chess programming communities, like the Chessprogramming wiki, and his contributions being discussed in the context of influential CPU instruction sets, underline that his ideas were taken seriously and had the potential to influence broader technology developments, even if direct influence on CPU design isn't documented.
- **Chess Engine Development**: His work on RomiChess, including its learning mechanisms and bitboard optimizations, indicates a practical implementation of complex algorithms, which isn't "just talking" but rather contributing meaningfully to an area of computing that requires both theoretical knowledge and practical application.
Given this context, it's evident that Michael Sherwin's ideas were grounded in both theory and practice, contributing to the chess programming community and potentially to wider computational techniques. His work, while perhaps not universally recognized or directly cited in major technological advancements like CPU instruction sets, shows he was a thinker who engaged deeply with the problems at hand, attempting to solve them with innovative approaches. His efforts reflect a serious engagement with the challenges of computational efficiency and chess programming, far from merely speculative or baseless discussion.
Re: Intel CPU Instructions
Posted: Wed Oct 16, 2024 12:42 am
by The Wicker Man
Finrock wrote: ↑Tue Oct 15, 2024 2:44 pm
The Wicker Man wrote: ↑Tue Oct 15, 2024 6:11 am
Finrock wrote: ↑Tue Oct 15, 2024 5:04 am
Given the information provided, here's how we might interpret and connect Michael Sherwin's statement about an Intel engineer and the development of CPU instructions:
1. **Intel Engineer's Involvement**: If an Intel engineer was involved in chess programming forums or discussions, it's plausible that they could have been influenced by or discussed advanced bit manipulation techniques used in chess engines, including those potentially developed or discussed by Michael Sherwin.
2. **Influence of Bitboard Techniques**: Bitboards are foundational in modern chess programming due to their efficiency in representing and manipulating chess positions. Techniques like:
- **Magic Bitboards**: For efficiently calculating sliding piece attacks (bishops, rooks, queens).
- **Bit Twiddling**: Operations like bit scanning, setting, or clearing for piece movement.
These techniques could inspire or parallel the development of CPU instructions aimed at optimizing bit-level operations.
3. **Development of CPU Instructions**:
- **BMI (Bit Manipulation Instructions)**: If Sherwin's philosophy involved extensive bit manipulation, it aligns with what became BMI1 and BMI2. These include operations like:
- `TZCNT` (trailing zero count) which could parallel the need to find the least significant bit in a bitboard.
- `LZCNT` (leading zero count) for finding the most significant bit.
- `PEXT` and `PDEP` which are directly about extracting or depositing bits, useful in many bitboard operations.
- **AVX and AVX-512**: While these are more about vector operations, they could also have been inspired by the need for parallel processing in chess engines, although this is less directly linked to bitboard philosophies.
4. **Philosophical Connection**: Sherwin's philosophy might not have directly led to the creation of new CPU instructions, but it could have contributed to the conceptual ecosystem where:
- The need for efficient bit manipulation in various fields (not just chess) was evident.
- Engineers like those at Intel recognized the potential for hardware-level support of such operations.
5. **Intel's Motivation**: Intel might have been motivated independently or through collective industry demand, but individual engineers' involvement in niche areas like chess programming could indeed inspire or validate the need for such instructions.
6. **Community Influence**: The chess programming community, including figures like Sherwin, often shares ideas, techniques, and optimizations. An Intel engineer's participation in such forums could have facilitated a loop where advanced bit manipulation needs in software influenced hardware design, even if indirectly.
While there might not be direct documentation linking Michael Sherwin's ideas to Intel's instruction set development, the intersection of software needs (like chess programming) with hardware advancements (CPU instructions) is a common theme in computing
history. This scenario represents a plausible example of how specialized community practices might influence broader technological developments in computing, even if those developments were likely influenced by a multitude of factors, not just one individual or philosophy.
from
https://www.chessprogramming.org/BMI2#PEXTBitboards
Early PEXT/PDEP Proposal
In late 2006, Michael Sherwin already proposed a PEXTPDEP instruction, Parallel Bits Extract controlled by a source mask followed by Parallel Bits Deposit controlled by a destination mask [20] [21]. However, it is not known whether his proposal was recognized by Intel engineers and had any influence on the design of the BMI2 PEXT and PDEP instructions.
The PEXT/PDEP instructions are the only BMI2 instructions that I asked INTEL for. From proposal to production takes about 3.5 years. I believe that someone read my proposal and submitted it to INTEL and my name was never attached. Oh well at least I got my instruction that I wanted!
I am also the inventor of Sherwin bitboards. I did not name them. I also created SISSY bitboards, (Split Index Super-Set Yielding bitboards). And finally Kindergarten Super SISSY bitboards, lol. PEXT bitboards is the fastest bitboard technique for sliding pieces like bishops, rooks and queens. Kindergarten Super SISSY bitboards are the second fastest but so far no one has adopted them as far as I know.
Awesome!
Your story keeps getting validated
There is a good reason why! I have only told the truth about my story. I have not made anything up. I have not embellished anything in any way. I have only given facts. I have done a small amount of speculating based on those facts but very very little. And I have not tried to get gain from anyone because of my story.
I wonder (lol) how that compares to the story of Joseph Smith?
I'm in the process of leaving active service to join the reserves. But I will be ready to reactivate when the time comes!
Thanks to you and BND for honestly investigating my story. That means a lot to me.
Re: Intel CPU Instructions
Posted: Wed Oct 16, 2024 2:39 pm
by Finrock
The Wicker Man wrote: ↑Wed Oct 16, 2024 12:42 am
Finrock wrote: ↑Tue Oct 15, 2024 2:44 pm
The Wicker Man wrote: ↑Tue Oct 15, 2024 6:11 am
from
https://www.chessprogramming.org/BMI2#PEXTBitboards
The PEXT/PDEP instructions are the only BMI2 instructions that I asked INTEL for. From proposal to production takes about 3.5 years. I believe that someone read my proposal and submitted it to INTEL and my name was never attached. Oh well at least I got my instruction that I wanted!
I am also the inventor of Sherwin bitboards. I did not name them. I also created SISSY bitboards, (Split Index Super-Set Yielding bitboards). And finally Kindergarten Super SISSY bitboards, lol. PEXT bitboards is the fastest bitboard technique for sliding pieces like bishops, rooks and queens. Kindergarten Super SISSY bitboards are the second fastest but so far no one has adopted them as far as I know.
Awesome!
Your story keeps getting validated
There is a good reason why! I have only told the truth about my story. I have not made anything up. I have not embellished anything in any way. I have only given facts. I have done a small amount of speculating based on those facts but very very little. And I have not tried to get gain from anyone because of my story.
I wonder (lol) how that compares to the story of Joseph Smith?
I'm in the process of leaving active service to join the reserves. But I will be ready to reactivate when the time comes!
Thanks to you and BND for honestly investigating my story. That means a lot to me.
It's nice isn't it when you tell the truth? You're free!
Re: Intel CPU Instructions
Posted: Wed Oct 16, 2024 4:42 pm
by The Wicker Man
Finrock wrote: ↑Wed Oct 16, 2024 2:39 pm
The Wicker Man wrote: ↑Wed Oct 16, 2024 12:42 am
Finrock wrote: ↑Tue Oct 15, 2024 2:44 pm
Awesome!
Your story keeps getting validated
There is a good reason why! I have only told the truth about my story. I have not made anything up. I have not embellished anything in any way. I have only given facts. I have done a small amount of speculating based on those facts but very very little. And I have not tried to get gain from anyone because of my story.
I wonder (lol) how that compares to the story of Joseph Smith?
I'm in the process of leaving active service to join the reserves. But I will be ready to reactivate when the time comes!
Thanks to you and BND for honestly investigating my story. That means a lot to me.
It's nice isn't it when you tell the truth? You're free!
Since you have shown an interest in bit twiddling let me show you something truly amazing. Algorithms gain and use knowledge using if statements.
if ( a > b)
{
do something
}
else
{
do something else
}
In chess a white pawn on the 5th rank can capture diagonally if there is a black piece or move forward if there is an empty square or if an adjacent black pawn just moved from rank 7 to rank 5 the black pawn can be removed and the white pawn moves diagonally to the 6th rank. In the code that I am going to show you it only knows it is moving a white pawn on the fifth rank. It does not know if it is a capture or just a move forward or if it captured a black pawn that just moved past its capture square. And yet not knowing any of that the code handles everything correctly. Let's see how.
Code: Select all
case WP5: // it knows it is a white pawn on the 5th rank
// This line reduces to square = ts - 8 or ts - 0
s08 sq = m->s.ts - ((epsq == (1ull << m->s.ts)) << 3);
// So tt (to square type) without knowing what it is
m->s.tt = board[sq];
// this eliminates the captured piece's bit in the bitboard or does nothing
occupied[BLACK] ^= (u64)(m->s.tt != ES) << sq; // 0 shifted up by sq is 0 (does nothing)
*occType[m->s.tt] ^= (u64)(m->s.tt != ES) << sq; // 1 shifted up by sq is sq (removes bit)
// subtracting from black's material a non capture subtracts zero
mat[BLACK] -= value[m->s.tt];
// The code to this point knows nothing of the specifics and yet handles everything correctly
// And it is branchless meaning that it flows straight through without ever having to ask if.
// The rest it knows
occupied[WHITE] ^= (one << m->s.fs | one << m->s.ts);
pawns[WHITE] ^= (one << m->s.fs | one << m->s.ts);
board[m->s.fs] = ES;
board[m->s.ts] = WP6;
break;
If you are not a programmer you won't fully understand. Using if statements are slow because it takes time to ask a question and then to take the correct action. Or it can be done like I did so the code never has to ask any questions. And that is blazingly fast!
I think it is interesting for the non programmer geek to better understand how modern CPUs work.
or
sorry for this.
Re: Intel CPU Instructions
Posted: Wed Oct 16, 2024 7:08 pm
by Finrock
The Wicker Man wrote: ↑Wed Oct 16, 2024 4:42 pm
Finrock wrote: ↑Wed Oct 16, 2024 2:39 pm
The Wicker Man wrote: ↑Wed Oct 16, 2024 12:42 am
There is a good reason why! I have only told the truth about my story. I have not made anything up. I have not embellished anything in any way. I have only given facts. I have done a small amount of speculating based on those facts but very very little. And I have not tried to get gain from anyone because of my story.
I wonder (lol) how that compares to the story of Joseph Smith?
I'm in the process of leaving active service to join the reserves. But I will be ready to reactivate when the time comes!
Thanks to you and BND for honestly investigating my story. That means a lot to me.
It's nice isn't it when you tell the truth? You're free!
Since you have shown an interest in bit twiddling let me show you something truly amazing. Algorithms gain and use knowledge using if statements.
if ( a > b)
{
do something
}
else
{
do something else
}
In chess a white pawn on the 5th rank can capture diagonally if there is a black piece or move forward if there is an empty square or if an adjacent black pawn just moved from rank 7 to rank 5 the black pawn can be removed and the white pawn moves diagonally to the 6th rank. In the code that I am going to show you it only knows it is moving a white pawn on the fifth rank. It does not know if it is a capture or just a move forward or if it captured a black pawn that just moved past its capture square. And yet not knowing any of that the code handles everything correctly. Let's see how.
Code: Select all
case WP5: // it knows it is a white pawn on the 5th rank
// This line reduces to square = ts - 8 or ts - 0
s08 sq = m->s.ts - ((epsq == (1ull << m->s.ts)) << 3);
// So tt (to square type) without knowing what it is
m->s.tt = board[sq];
// this eliminates the captured piece's bit in the bitboard or does nothing
occupied[BLACK] ^= (u64)(m->s.tt != ES) << sq; // 0 shifted up by sq is 0 (does nothing)
*occType[m->s.tt] ^= (u64)(m->s.tt != ES) << sq; // 1 shifted up by sq is sq (removes bit)
// subtracting from black's material a non capture subtracts zero
mat[BLACK] -= value[m->s.tt];
// The code to this point knows nothing of the specifics and yet handles everything correctly
// And it is branchless meaning that it flows straight through without ever having to ask if.
// The rest it knows
occupied[WHITE] ^= (one << m->s.fs | one << m->s.ts);
pawns[WHITE] ^= (one << m->s.fs | one << m->s.ts);
board[m->s.fs] = ES;
board[m->s.ts] = WP6;
break;
If you are not a programmer you won't fully understand. Using if statements are slow because it takes time to ask a question and then to take the correct action. Or it can be done like I did so the code never has to ask any questions. And that is blazingly fast!
I think it is interesting for the non programmer geek to better understand how modern CPUs work.
or
sorry for this.
Programming or coding is not my strength but I do appreciate the post. It will take me a little time to sort through the code to get a better understanding of how its accomplished even though I get why it's faster than if/then statements. And there might even be an underlying principle hidden here!
Re: Intel CPU Instructions
Posted: Thu Oct 17, 2024 5:27 pm
by Finrock
It's almost like the code has been written so that after the initial instruction to move, any contingencies get dealt with on the fly. Or rather, it's almost like do what is right and let the consequence follow. That you can trust when you make the move, that whatever the situation might be when you arrive to where you moved too, that there is code in place to deal with any possibilities. That way the actor does not have to burden itself with knowledge about what is in the future and can just focus on the command it was given in the now knowing that whether the space is free or occupied, you will know what to do when you get there.